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ltc4361-1/ltc4361-2 1 436112fb typical a pplica t ion descrip t ion overvoltage/overcurrent protection controller a pplica t ions n usb protection n handheld computers n cell/smart phones n mp3/mp4 players n digital cameras n 2.5v to 5.5v operation n overvoltage protection up to 80v n no input capacitor or tvs required for most applications n 2% accurate 5.8v over voltage threshold n 10% accurate 50mv overcurrent circuit breaker n <1 s overvoltage turn-off, gentle shutdown n controls n-channel mosfet n adjustable power-up dv/dt limits inrush current n reverse voltage protection n power good output n low current shutdown n latchoff (ltc4361-1) or auto-retry (ltc4361-2) after over current n available in 8-lead thinsot? and 8-lead (2mm 2mm) dfn packages the lt c ? 4361 overvoltage / overcurrent protection control- ler safeguards 2.5 v to 5.5 v systems from input supply overvoltage. it is designed for portable devices with multiple power supply options including wall adaptors, car battery adaptors and usb ports. the ltc4361 controls an external n-channel mosfet in series with the input power supply. during overvoltage transients, the ltc4361 turns off the mosfet within 1s, isolating downstream components from the input supply. inductive cable transients are absorbed by the mosfet and load capacitance. in most applications, the ltc4361 provides protection from transients up to 80 v without requiring transient voltage suppressors or other external components. the ltc4361 has a delayed start- up and adjustable dv/ dt ramp- up for inrush current limiting. a pwrgd pin provides power good monitoring for v in . the ltc4361 features a soft shutdown controlled by the on pin and drives an optional external p- channel mosfet for negative voltage protection. following an overvoltage condition, the ltc4361 automati- cally restarts with a start- up delay. after an overcurrent fault, the ltc4361-1 remains off while the ltc4361-2 automatically restarts after a 130ms start- up delay. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and thinsot, hot swap, no r sense and powerpath are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. output protected from overvoltage at input protection from overvoltage and overcurrent gate si1470dh 0.025 sense in 436112 ta01a v out 5v 1.5a v in 5v ltc4361 on out pwrgd gnd c out v gate 10v/div v in , v out 5v/div 0.5s/div 436112 ta01b si1470dh c out = 10f v out v in fea t ures
ltc4361-1/ltc4361-2 2 436112fb bias supply voltage ( in ) ............................ C0. 3 v to 85 v input voltages sense ................................................... C0. 3 v to 85 v out , on ................................................... C 0.3 v to 9v output voltages pwrgd .................................................... C 0.3 v to 9v gate ( note 3) ........................................ C 0.3 v to 15 v gatep .................................................... C 0.3 v to 85 v in to gatep ........................................... C 0.3 v to 10 v (notes 1, 2) o r d er i n f orma t ion lead free finish tape and reel (mini) tape and reel part marking* package description temperature range ltc4361cts8-1#trmpbf ltc4361cts8-1#trpbf ltdwn 8-lead plastic tsot-23 0c to 70c ltc4361cts8-2#trmpbf ltc4361cts8-2#trpbf ltfmn 8-lead plastic tsot-23 0c to 70c ltc4361its8-1#trmpbf ltc4361its8-1#trpbf ltdwn 8-lead plastic tsot-23 C40c to 85c ltc4361its8-2#trmpbf ltc4361its8-2#trpbf ltfmn 8-lead plastic tsot-23 C40c to 85c ltc4361hts8-1#trmpbf ltc4361hts8-1#trpbf ltdwn 8-lead plastic tsot-23 C40c to 125c ltc4361hts8-2#trmpbf ltc4361hts8-2#trpbf ltfmn 8-lead plastic tsot-23 C40c to 125c ltc4361cdc-1#trmpbf ltc4361cdc-1#trpbf ldwp 8-lead (2mm 2mm) plastic dfn 0c to 70c ltc4361cdc-2#trmpbf ltc4361cdc-2#trpbf lfmp 8-lead (2mm 2mm) plastic dfn 0c to 70c ltc4361idc-1#trmpbf ltc4361idc-1#trpbf ldwp 8-lead (2mm 2mm) plastic dfn C40c to 85c ltc4361idc-2#trmpbf ltc4361idc-2#trpbf lfmp 8-lead (2mm 2mm) plastic dfn C40c to 85c ltc4361hdc-1#trmpbf ltc4361hdc-1#trpbf ldwp 8-lead (2mm 2mm) plastic dfn C40c to 125c ltc4361hdc-2#trmpbf ltc4361hdc-2#trpbf lfmp 8-lead (2mm 2mm) plastic dfn C40c to 125c trm = 500 pieces. *temperature grades are identified by a label on the shipping container. consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ a bsolu t e m aximum r a t ings p in c on f igura t ion operating temperature range ltc 4361 c ................................................ 0 c to 70 c ltc 4361 i ............................................. C4 0 c to 85 c ltc 4361 h .......................................... C 40 c to 125 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) tso t ................................................................. 30 0 c on 1 out 2 gatep 3 gnd 4 8 pwrgd 7 gate 6 sense 5 in top view ts8 package 8-lead plastic tsot-23 t jmax = 125c, ja = 195c/w top view gnd gatep out on in sense gate pwrgd dc package 8-lead (2mm 2mm) plastic dfn 9 4 1 2 3 6 5 7 8 t jmax = 125c, ja = 102c/w exposed pad (pin 9) is gnd, connection optional
ltc4361-1/ltc4361-2 3 436112fb e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 5v, v on = 0v, unless otherwise noted. symbol parameter conditions min typ max units supplies v in input voltage range l 2.5 80 v v in(uvl) input undervoltage lockout v in rising l 1.8 2.1 2.47 v i in input supply current v on = 0v l 220 400 a v on = 2.5v l 1.5 10 a thresholds v in(ov) in pin overvoltage threshold v in rising l 5.684 5.8 5.916 v v in(ovl) in pin overvoltage recovery threshold v in falling l 5.51 5.7 5.85 v ?v ov overvoltage hysteresis l 25 100 260 mv ?v oc overcurrent threshold v in C v sense l 45 50 55 mv external gate drive ?v gate external n-channel mosfet gate drive (v gate C v out ) 2.5v v in < 3v, i gate = C1a 3v v in < 5.5v, i gate = C1a l l 3.5 4.5 4.5 6 6 7.9 v v v gate(th) gate high threshold for pwrgd status v in = 3.3v v in = 5v l l 5.7 6.7 6.3 7.2 6.8 7.8 v v i gate(up) gate pull-up current v gate = 1v l C4.5 C10 C15 a v gate(up) gate ramp-up v gate = 1v to 7v l 1.3 3 4.5 v/ms i gate(fst) gate pull-down current fast turn-off, v in = 6v, v gate = 9v (c-, i-grade) ( h-grade) l l 15 12 30 30 60 60 ma ma i gate(dn) gate pull-down current v on = 2.5v, v gate = 9v l 5 40 80 a input pins i sense(in) sense input current v sense = 5v 10 na i out(in) out input current v out = 5v, v on = 0v v out = 5v, v on = 2.5v l l 5 10 0 20 3 a a v on(th) on input threshold l 0.4 1.5 v i on on pull-down current v on = 2.5v l 2 5 10 a output pins v gatep(clp) in to gatep clamp voltage v in = 8v to 80v l 5 5.8 7.9 v r gatep gatep resistive pull-down v gatep = 3v l 0.6 2 3.2 m v pwrgd (ol) pwrgd output low voltage v in = 5v, i pwrgd = 3ma (c-, i-grade) ( h-grade) l l 0.23 0.23 0.4 0.5 v v r pwrgd pwrgd pull-up resistance to out v in = 6.5v, v pwrgd = 1v l 220 500 800 k delay t on gate on delay v in high to i gate = C5a l 50 130 219 ms t off gate off propagation delay v in = step 5v to 6.5v to pwrgd high v in C v sense = step 0mv to 100mv l l 5 0.25 10 1 20 s s t pwrgd pwrgd delay v in = step 5v to 6.5v v gate > v gate(th) to pwrgd low l l 25 0.25 65 1 105 s ms t on(off) on high to gate off v on = step 0v to 2.5v l 2 5 s note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to gnd unless otherwise specified. note 3: an internal clamp limits v gate to a minimum of 4.5v above v out . driving this pin to voltages beyond this clamp may damage the device.
ltc4361-1/ltc4361-2 4 436112fb typical p er f ormance c harac t eris t ics pwr gd voltage vs pwr gd current gate off propagation delay vs overdrive normal start-up sequence gate slow ramp-up entering sleep mode input supply current vs input voltage gate drive vs gate current gate fast pull-down current vs temperature v in (v) 1 0.1 i in (a) 1 100 1000 10000 100 436112 g01 10 10 v on = 0v v on = 2.5v i gate (a) 0 0 ?v gate (v) 4 3 2 1 6 7 8 4 8 10 12 436112 g02 5 2 6 v in = 5v v in = 3v v in = 2.5v temperature (c) ?50 20 i gate(fst) (ma) 25 30 35 40 ?25 0 25 v in = 6v v gate = 9v 50 436112 g03 75 125100 i pwrgd (ma) 0 0 v pwrgd(ol) (mv) 200 100 300 400 500 1 2 3 4 436112 g04 5 v ovdrv (v) 0 0 t off (s) 2 1 4 0.5 1 1.5 436112 g05 2 6 8 3 5 7 2.5 v in = step 5v to (v in(ov) + v ovdrv ) v in 5v/div v gate 10v/div v out 5v/div i cable 0.5a/div 20ms/div 436112 g07 figure 5 circuit r in = 150m, l in = 0.7h r sense = 25m load = 10, c out = 10f v in 5v/div v gate 10v/div v out 5v/div i cable 0.5a/div 1ms/div 436112 g08 figure 5 circuit r in = 150m, l in = 0.7h r sense = 25m load = 10, c out = 10f v on 5v/div v gate 10v/div v out 5v/div i cable 0.5a/div 50s/div 436112 g09 figure 5 circuit r in = 150m, l in = 0.7h r sense = 25m load = 10, c out = 10f t a = 25c, v in = 5v, v on = 0v, unless otherwise noted. v in (v) 2.5 4 v gate /vg gate(th) (v) 6 5 8 3.5 4 3 54.5 436112 g06 5.5 10 12 7 9 11 6 v gate v gate(th) v in = v out gate voltage and gate high threshold (for pwr gd status) vs input voltage
ltc4361-1/ltc4361-2 5 436112fb p in func t ions exposed pad ( dfn): ground. connection to pcb is optional. gate: gate drive for external n-channel mosfet. an internal charge pump provides a 10 a pull-up current to charge the gate of the external n-channel mosfet. an additional ramp circuit limits the gate ramp rate when turning on to 3 v/ms. for slower ramp rates, connect an external capacitor from gate to gnd. an internal clamp limits gate to 6 v above the out pin voltage. an internal gate high comparator controls the pwrgd pin. gatep : gate drive for external p- channel mosfet. gatep connects to the gate of an optional external p- channel mos- fet to protect against negative voltages at in. this pin is internally clamped to 5.8 v below v in . an internal 2 m resis- tor connects this pin to ground. connect to in if not used. gnd: device ground. in: supply voltage input. connect this pin to the input power supply. this pin has an overvoltage threshold of 5.8v. after an overvoltage event, this pin must fall below v in(ov) C ?v ov to release the overvoltage lockout. dur- ing lockout, gate is held low and the pwrgd pull-down releases. on: on control input. a logic low at on enables the ltc4361. a logic high at on activates a low current pull- down at the gate pin and causes the ltc4361 to enter a low current sleep mode. an internal 5 a current pulls on down to ground. connect to ground or leave open if unused. out : output voltage sense input for gate clamp. connect to the source of the external n-channel mosfet to sense the output voltage for gate to out clamp. pwr gd : power good status. open-drain output with internal 500 k resistive pull-up to out. pulls low 65ms after gate ramps above v gate(th) . sense: current sense input. connect a sense resistor between in and sense. an overcurrent protection circuit turns off the n-channel mosfet when the voltage across the sense resistor exceeds 50mv for more than 10s.
ltc4361-1/ltc4361-2 6 436112fb o pera t ion mobile devices like cell phones and mp3/mp4 players have highly integrated subsystems fabricated from deep submi- cron cmos processes. the small form factor is accompanied by low absolute maximum voltage ratings. the sensitive electronics are susceptible to damage from transient or dc overvoltage conditions from the power supply. failures or faults in the power adaptor can cause an overvolt - age event. so can hot- plugging an ac adaptor into the power input of the mobile device ( see lt c application note 88). today s mobile devices derive their power supply or recharge their internal batteries from multiple alternative inputs like ac wall adaptors, car battery adaptors and usb ports. a user may unknowingly plug in the wrong adaptor, damaging the device with a high or even a negative power supply voltage. the ltc4361 protects low voltage electronics from these overvoltage conditions by controlling a low cost external n - channel mosfet configured as a pass transistor. at power-up (v in > 2.1 v), a start-up delay cycle begins. any overvoltage condition causes the delay cycle to continue until a safe voltage is present. when the delay cycle com- pletes, an internal high side switch driver slowly ramps up the mosfet gate, powering up the output at a controlled rate and limiting the inrush current to the output capacitor. if the voltage at the in pin exceeds 5.8v (v in(ov) ), gate is pulled low quickly to protect the load. the incoming power supply must remain below 5.7 v (v in(ov) C ?v ov ) for the duration of the start-up delay to restart the gate ramp-up. a sense resistor placed between in and sense implements an overcurrent protection with a 50 mv trip threshold and a 10 s glitch filter. after an overcurrent, the ltc4361- 1 latches off while the ltc4361-2 restarts following a 130ms delay. the ltc4361 has a cmos compatible on input. when driven low, the part is enabled. when driven high, the external n-channel mosfet is turned off and the supply current of the ltc4361 drops to 1.5 a. the pwrgd pull- down releases during this low current sleep mode, uvlo, overvoltage or overcurrent and the subsequent 130ms start-up delay. after the start-up delay, gate starts its slow ramp-up and ramps higher than v gate(th) to trigger a 65 ms delay cycle. when that completes, pwrgd pulls low.the ltc4361 has a gatep pin that drives an optional external p-channel mosfet to provide protection against negative voltages at in. b lock diagram ? + gnd 436112 bd 10a on out pwrgd 5.8v 500k gate control charge pump overcurrent comparator 50mv + ? ? + 5.8v 5.7v overvoltage comparator in sense 1.8m 200k 5.8v gatep 5a 1v + ? v gate(th) gate high comparator + ?
ltc4361-1/ltc4361-2 7 436112fb the typical ltc4361 application protects 2.5 v to 5.5v systems in portable devices from power supply overvolt- age. the basic application circuit is shown in figure 1. device operation and external component selection is discussed in detail in the following sections. a pplica t ions i n f orma t ion figure 1. protection from input overvoltage and overcurrent gate m1 si1470dh r sense 0.025 sense in 436112 f01 v out 5v 1.5a v in 5v ltc4361 out pwrgd on gnd c out 10f the gate ramp rate is limited to 3 v/ms. v out follows at a similar rate which results in an inrush current into the load capacitor c out of: i inrush = c out ? dv gate dt = c out ? 3 ma/f [ ] the servo loop is compensated by the parasitic capaci- tance of the external mosfet. no further compensation components are normally required. in the case where the parasitic capacitance is less than 100 pf, a 100pf compensation capacitor between gate and ground may be required. an even slower gate ramp and lower inrush current can be achieved by connecting an external capacitor, c g , from gate to ground. the voltage at gate then ramps up with a slope equal to 10 a/c g [ v/s ]. choose c g using the formula: c g = 10a i inrush ? c out overvoltage when power is first applied, v in must remain below 5.7v (v in(ov) C ?v ov ) for more than 130 ms before gate is ramped up to turn on the mosfet. if v in then rises above 5.8v (v in(ov) ), the overvoltage comparator activates the 30ma fast pull-down on gate within 1 s. after an over- voltage condition, the mosfet is held off until v in once again remains below 5.7v for 130ms. overcurrent the overcurrent comparator protects the mosfet from excessive current. it trips when the sense pin falls more than 50 mv below in for 10 s. when the overcurrent comparator trips, gate is pulled low quickly and the pwrgd pull- down releases. the ltc4361 - 2 automatically tries to apply power again after a 130 ms start-up delay. start-up when v in is less than the undervoltage lockout level of 2.1v , the gate driver is held low and the pwrgd pull- down is high impedance. when v in rises above 2.1 v and on is held low, a 130 ms delay cycle starts. any undervoltage or overvoltage event at in (v in < 2.1 v or v in > 5.7 v) restarts the delay cycle. this delay allows the n-channel mosfet to isolate the output from any input transients that occur at start-up. when the delay cycle completes, gate starts its slow ramp-up. gate control an internal charge pump provides a gate overdrive greater than 3.5 v when 2.5v v in < 3 v. if v in 3 v, the gate drive is guaranteed to be greater than 4.5 v. this allows the use of logic-level n-channel mosfets. an internal 6 v clamp between gate and out protects the mosfet gate.
ltc4361-1/ltc4361-2 8 436112fb applica t ions in f orma t ion the ltc4361-1 has an internal latch that maintains this off state until it is reset. to reset this latch, cycle in be- low 2.1v (v in(uvl) ) or on above 1.5v (v on(th) ) for more than 500 s. after reset, the ltc4361-1 goes through the start-up cycle. in applications not requiring the overcurrent protection, tie the sense pin to the in pin. to implement an overcurrent threshold i trip , choose r sense using the formula: r sense = ? v oc i trip after choosing the r sense , keep in mind that: i trip(max) = ? v oc(max) r sense(min) i trip(min) = ? v oc(min) r sense(max) pwr gd output pwrgd is an active low output with a mosfet pull-down to ground and a 500 k resistive pull-up to out. the pwrgd pin pull-down releases during the low current sleep mode (invoked by on high), uvlo, overvoltage or overcurrent and the subsequent 130 ms start-up delay. after the start- up delay, gate starts its slow ramp-up and control of the pwrgd pull- down passes on to the gate high comparator. v gate > v gate(th) for more than 65 ms asserts the pwrgd pull-down and v gate < v gate(th) releases the pull-down. the pwrgd pull-down is capable of sinking up to 3 ma of current allowing it to drive an optional led. to interface pwrgd to another i/o rail, connect a resistor from pwrgd to the i/o rail with a resistance low enough to override the internal 500 k pull-up to out. figure 2 details pwrgd behavior for a ltc4361-2 with 1 k pull-up to 5 v at pwrgd . in out gate on pwrgd v gate(th) v gate(th) v gate(th) v gate(th) v gate(th) v in(uvl) i cable oc threshold 10s (not to scale) 436112 f02 v in(ov) ??v ov start-up from uvlo restart from ov ov restart from on on restart from oc oc v in(ov) 130ms 65ms 130ms 65ms 130ms 65ms 130ms 65ms figure 2. pwr gd behavior
ltc4361-1/ltc4361-2 9 436112fb a pplica t ions i n f orma t ion on input on is a cmos compatible, active low enable input. it has a default 5 a pull-down to ground. connect this pin to ground or leave open to enable normal device operation. if it is driven high while the external mosfet is turned on, gate is pulled low with a weak pull-down current (40a) to turn off the external mosfet gradually, minimizing input voltage transients. the ltc4361 then goes into a low current sleep mode, drawing only 1.5a at in. when on goes back low, the part restarts with a 130 ms delay cycle. gatep control gatep has a 2 m resistive pull-down to ground and a 5.8v zener clamp in series with a 200 k resistor to in. it con- trols the gate of an optional external p-channel mosfet to provide negative voltage protection. the 2 m resistive pull-down turns on the mosfet once v in C v gatep is more than the mosfet gate threshold voltage. the in to gatep zener protects the mosfet from gate overvoltage by clamping its v gs to 5.8v when v in goes high. mosfet configurations and selection the ltc4361 can be used with various external mosfet configurations ( see figure 3). the simplest configuration is a single n-channel mosfet. it has the lowest r ds(on) and voltage drop and is thus the most power efficient solution. when gate is pulled to ground, the n-channel mosfet can isolate out from a positive voltage at in up to the bv dss of the n-channel mosfet. however, reverse current can still flow from out to in via the parasitic body diode of the n-channel mosfet. for near zero reverse- leakage current protection when gate is pulled to ground, back-to-back n-channel mosfets can be used. adding an additional p-channel mosfet controlled by gatep provides negative input voltage protection down to the bv dss of the p-channel mosfet. another configuration consists of a p-channel mosfet controlled by gatep and a n-channel mosfet controlled by gate. this provides protection against overvoltage and negative voltage but not reverse current. figure 3. mosfet configurations gatep overvoltage, reverse- current protection negative voltage protection gate overvoltage, reverse- current protection gate gate gatep supply supply supply supply 436112 f03 overvoltage protection overvoltage protection m1 m1 m3 m1 m2 m1 m2 m3 negative voltage protection gate out out out in r sense sense out in r sense sense in r sense sense in r sense sense
ltc4361-1/ltc4361-2 10 436112fb a pplica t ions i n f orma t ion figure 4. 20v hot-plug into a 10f capacitor figure 5. 20v hot-plug into the ltc4361 + load 436112 f04a mobile device wall adaptor ac/dc c out in l in r in cable i cable v in 10v/div i cable 20a/div 5s/div 436112 f04b r in = 150m, l in = 0.7h load = 10, c out = 10f + load ltc4361 m1 si1470dh gate gnd 436112 f05a mobile device wall adaptor ac/dc c out sense out in in out l in r in r sense cable i cable v in 10v/div v out 1v/div i cable 20a/div 5s/div 436112 f05b r in = 150m, l in = 0.7h, r sense = 25m load = 10, c out = 10f input transients figure 4 shows a typical setup when an ac wall adaptor charges a mobile device. the inductor l in represents the lumped equivalent inductance of the cable and the emi filter found in some wall adaptors. r in is the lumped equivalent resistance of the cable, adaptor output capacitor esr and the connector contact resistance. l in and r in form an lc tank circuit with any capacitance at in. if the wall adaptor is powered up first, plugging the wall adaptor output to in does the equivalent of applying a voltage step to this lc circuit. the resultant voltage overshoot at in can rise to twice the dc output voltage of the wall adaptor as shown in figure 4. figure 5 shows the 20 v adaptor output applied to the ltc4361. due to the low capacitance at the in pin, the plug-in transient has been brought down to a manageable level.
ltc4361-1/ltc4361-2 11 436112fb a pplica t ions i n f orma t ion as the in pin can withstand up to 80 v, a high voltage n-channel mosfet can be used to protect the system against rugged abuse from high transient or dc voltages up to the bv dss of the mosfet. figure 6 shows a 50v input plugged into the ltc4361 controlling a 60 v rated mosfet. input transients also occur when the current through the cable inductance changes abruptly. this can happen when the ltc4361 turns off the n-channel mosfet rapidly in an overvoltage or overcurrent event. figure 7 shows an input transient after an overcurrent. the current in l in will cause v in to overshoot and avalanche the n-channel mosfet to c out . typically, in will be clamped to a voltage of v out + 1.3 ? ( bv dss of si1470dh ) = 45 v. this is well below the 85v absolute maximum voltage rating of the ltc4361. the single, nonrepetitive, pulse of energy (e as ) absorbed by the mosfet during this avalanche breakdown with a peak current i as is approximated by the formula: e as = 0.5 ? l in ? i as 2 for l in = 0.7 h and i as = 4a , then e as = 5.6j . this is within the i as and e as capabilities of most mosfets including the si1470dh. so in most instances, the ltc4361 can ride through such transients without a bypass capacitor, transient voltage suppressor or other external components at in. note that if an in bypass capacitor is used, the v in transients will overshoot less but last longer. if v in dips below v in(uvl) for more than 10 s, the internal latch-off latch in the ltc4361-1 could be inadvertently reset. figure 6. 50v hot-plug into the ltc4361 figure 7. overcurrent turn-off and resulting input transient v in 20v/div v out 1v/div i cable 5a/div 5s/div 436112 f06 fdc5612 r in = 150m, l in = 0.7h r sense = 25m, load = 10, c out = 10f v in 20v/div v gate 10v/div v out 5v/div i cable 5a/div 2s/div 436112 f07 figure 5 circuit r in = 150m, l in = 0.7h r sense = 25m, load = 10, c out = 10f
ltc4361-1/ltc4361-2 12 436112fb figure 10. layout for n-channel mosfet configuration figure 8. setup for testing 20v plugged into 5v system figure 9. overvoltage protection waveforms when 20v plugged into 5v system load 436112 f08 out m1 si1470dh c out in r sense l in d1 b160 r in 20v wall adapter 5v usb r1 100k ltc4361 gnd gate + ? + ? i cable sense in out v in 20v/div v gate 10v/div v out 5v/div i cable 10a/div 1s/div 436112 f09 figure 8 circuit r in = 150m l in = 2h, r sense = 25m, load = 10 c out = 10f (16v, size 1210) ltc4361 436112 f10 8 6 5 1 7 2 3 4 si1470dh out in supply gnd r sense 1 2 3 6 5 4 figure 8 shows a particularly severe situation which can occur in a mobile device with dual power inputs. a 20v wall adaptor is mistakenly hot-plugged into the 5 v device with the usb input already live. as shown in figure 9, a large current can build up in l in to charge up c out . when the n-channel mosfet shuts off, the energy stored in l in is dumped into c out , causing a large 40 v input transient. the ltc4361 limits this to a 1 v rise in the output voltage. if the ?v out due to the discharge of the energy in l in into c out is not acceptable or the avalanche capability of the mosfet is exceeded, an additional external clamp such as the smaj24a can be placed between in and gnd. c out is the decoupling capacitor of the protected circuits and its value will largely be determined by their requirements. using a larger c out will work with l in to slow down the dv/dt at out, allowing time for the ltc4361 to shut off the mosfet before v out overshoots to a dangerous volt- age. a larger c out also helps to lower the ? v out due to the discharge of the energy in l in if the mosfet bv dss is used as an input clamp. layout considerations figure 10 shows an example pcb layout for the ltc4361 (ts8 package) with a single n-channel mosfet (sc70 package) and a 0603 size sense resistor. keep the traces to the n-channel mosfet wide and short. the pcb traces associated with the power path through the n-channel mosfet should have low resistance. use kelvin connec- tions to r sense for an accurate overcurrent threshold. a pplica t ions i n f orma t ion
ltc4361-1/ltc4361-2 13 436112fb 2.00 0.10 (4 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 0.64 0.10 (2 sides) 0.75 0.05 r = 0.115 typ r = 0.05 typ 1.37 0.10 (2 sides) 1 4 8 5 pin 1 bar top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dc8) dfn 0409 reva 0.23 0.05 0.45 bsc 0.25 0.05 1.37 0.05 (2 sides) recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.64 0.05 (2 sides) 1.15 0.05 0.70 0.05 2.55 0.05 package outline 0.45 bsc pin 1 notch r = 0.20 or 0.25 45 chamfer dc8 package 8-lead plastic dfn (2mm 2mm) (reference ltc dwg # 05-08-1719 rev a) p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
ltc4361-1/ltc4361-2 14 436112fb 1.50 ? 1.75 (note 4) 2.80 bsc 0.22 ? 0.36 8 plcs (note 3) datum ?a? 0.09 ? 0.20 (note 3) ts8 tsot-23 0710 rev a 2.90 bsc (note 4) 0.65 bsc 1.95 bsc 0.80 ? 0.90 1.00 max 0.01 ? 0.10 0.20 bsc 0.30 ? 0.50 ref pin one id note: 1. dimensions are in millimeters 2. drawing not to scale 3. dimensions are inclusive of plating 4. dimensions are exclusive of mold flash and metal burr 5. mold flash shall not exceed 0.254mm 6. jedec package reference is mo-193 3.85 max 0.40 max 0.65 ref recommended solder pad layout per ipc calculator 1.4 min 2.62 ref 1.22 ref ts8 package 8-lead plastic tsot-23 (reference ltc dwg # 05-08-1637 rev a) p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings.
ltc4361-1/ltc4361-2 15 436112fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 01/11 revised conditions for v gate(clp) and t off in electrical characteristics section revised gate control in applications information section 3 7 b 05/12 added h-grade order information change to electrical characteristics input undervoltage lockout added v in(ovl) specifications change to electrical characteristics overvoltage hysteresis change to electrical characteristics gate pull-up and pull-down current change to electrical characteristics gate ramp-up added i sense(in) specifications change to electrical characteristics on pull-down current change to electrical characteristics in to gatep clamp voltage change to electrical characteristics gatep resistive pull-down change to electrical characteristics pwrgd pull-up resistance to out change to electrical characteristics gate on delay change to electrical characteristics pwrgd delay replaced gate fast pull-down current vs temperature curve added pcb trace to short pin 3 to pin 5 in figure 10 added packaging link 2 3 3 3 3 3 3 3 3 3 3 3 3 4 12 13, 14
ltc4361-1/ltc4361-2 16 436112fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2010 lt 0512 rev b ? printed in usa typical a pplica t ion 5v system protected from 24v power supplies, overcurrent and reverse current r ela t e d p ar t s part number description comments ltc2935 ultralow power supervisor with eight pin-selectable thresholds 500na quiescent current, 2mm w 2mm 8-lead dfn and tsot-23 packages lt3008 20ma, 45v, 3a i q micropower ldo 280mv dropout voltage, low i q : 3a, v in = 2.0v to 45v, v out = 0.6v to 39.5v; thinsot and 2mm w 2mm dfn-6 packages lt3009 20ma, 3a i q micropower ldo 280mv dropout voltage, low i q : 3a, v in = 1.6v to 20v, v out = 0.6v to 19.5v; thinsot and sc-70 packages ltc3576/ ltc3576-1 switching usb power manager with usb otg + triple step-down dc/dcs complete multifunction pmic: bi-directional switching power manager + 3 bucks + ldo ltc4090/ ltc4090-5 high voltage usb power manager with ideal diode controller and high efficiency li-ion battery charger high efficiency 1.2a charger from 6v to 38v (60v max) input charges single cell li-ion batteries directly from a usb port ltc4098 usb-compatible switchmode power manager with ovp high v in : 38v operating, 60v transient; 66v ovp. 1.5a max charge current from wall, 600ma charge current from usb ltc4210 single channel, low voltage hot swap? controller operates from 2.7v to 16.5v, active current limiting, sot23-6 ltc4213 no r sense ? electronic circuit breaker controls load voltages from 0v to 6v. 3 selectable circuit breaker thresholds. dual level over current fault protection lt4356 surge stopper- overvoltage/overcurrent protection regulator wide operation range: 4v to 80v. reverse input protection to C60v. adjustable output clamp voltage LTC4411 sot-23 ideal diode 2.6a forward current, 28mv regulated forward voltage ltc4412 2.5v to 28v, low loss powerpath? controller in thinsot more efficient than diode-oring, automatic switching between dc sources, simplified load sharing ltc4413-1/ ltc4413-2 dual 2.6a, 2.5v to 5.5v fast ideal diodes in 3mm w 3mm dfn 130m on resistance, low reverse leakage current, 18mv regulated forward voltage (ltc4413-2 with overvoltage protection sensor) 5v system protected from 24v power supplies and overcurrent si3590dv r sense 0.05 436112 ta02 v out 5v 0.5a c out 10f m2 m1 d1 ln1351ctr r1 1k v io 5v v in 5v gate sense in ltc4361 gatep out pwrgd on gnd m2 si1471dh fdc6561an r sense 0.05 436112 ta03 v out 5v 0.5a c out 10f m1 m3 d1 ln1351ctr r1 1k v io 5v v in 5v gate sense in ltc4361 gatep out pwrgd on gnd

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